1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to an integrated circuit which employs staggered interconnects formed using a damascene process. The interconnect lines are produced such that one interconnect line is configured in a plane dissimilar from, and laterally spaced between, a pair of interconnect lines. By staggering the interconnect lines, a higher density interconnect structure can be produced with minimal electric field coupling between the interconnect lines.
2. DESCRIPTION OF THE RELEVANT ART
An integrated circuit includes numerous conductors extending across the topography of a monolithic substrate. A set of interconnect lines (or conductors) which serve to electrically connect two or more components within a system is generally referred to as a "bus". A collection of voltage levels are forwarded across the conductors to allow proper operation of the components. For example, a microprocessor is connected to memories and input/output devices by certain bus structures. There are numerous types of busses which are classified according to their operation. Examples of well-known types of busses include address busses, data busses and control busses.
Conductors within a bus generally extend partially parallel to each other across the semiconductor topography. The conductors are isolated from each other and from underlying conductive elements by a dielectric, a suitable dielectric being, for example, silicon dioxide ("oxide"). Conductors are thereby lithographically patterned across the semiconductor topography, wherein the topography comprises a substrate with a dielectric placed thereon. The topography can also include one or more layers of conductors which are covered by a dielectric material. The layers of conductors overlaid with a dielectric present a topography upon which a subsequent layer of conductors can be patterned.
Conductors are made from an electrically conductive material, a suitable material includes Al, Ti, Ta, W, Mo, polysilicon, or a combination thereof. Substrate includes any type of material which can retain dopant ions and the isolated conductivity regions brought about by those ions. Typically, substrate is a silicon-based material which receives p-type or n-type ions.
Generally speaking, interconnect lines (or conductors) are fashioned upon the topography and dielectrically spaced above an underlying conductor or substrate by a dielectric thickness T.sub.d1. Each conductor is dielectrically spaced from other conductors within the same level of conductors (i.e., substantially coplanar conductors) by a distance T.sub.d2. Accordingly, capacitance between vertically spaced conductors, or intralevel capacitance C.sub.LS is determined as follows: EQU C.sub.LS .apprxeq.eW.sub.L L/T.sub.d1 (Eq. 1)
Further, capacitance between horizontally spaced, substantially coplanar conductors, or interlevel capacitance C.sub.LL is determined as follows: EQU C.sub.LL eT.sub.c L/T.sub.d2 (Eq. 2)
where e is the permittivity of the dielectric material (the dielectric material between the conductor and substrate or the dielectric material between conductors), W.sub.L is the conductor width, and L is the conductor length. Resistance of the conductor is calculated as follows: EQU R=(rL)/W.sub.L T.sub.C (Eq. 3)
where r represents resistivity of the conductive material, and T.sub.c is the interconnect thickness. Combinations of equations 1 and 3, and/or equations 2 and 3 indicate as follows the propagation delay or coupling of a conductor to an adjacent conductor: EQU RC.sub.LS.apprxeq. reL.sup.2 /T.sub.c T.sub.d1 EQU RC.sub.LL.apprxeq. reL.sup.2 /W.sub.L T.sub.d1
Propagation delay is an important characteristic of an integrated circuit since it limits the speed (frequency) at which the circuit or circuits can operate. The shorter the propagation delay, the higher the speed of the circuit or circuits. It is therefore important that propagation delay and/or capacitive coupling be minimized as much as possible given the geometric constraints of the semiconductor topography.
Propagation delay is shown to be a function of both capacitance C.sub.LS as well as capacitance C.sub.LL. In general, C.sub.LS can be minimized by placing the conductor on one plane substantially perpendicular to conductors on another plane. The cross-over points are therefore minimal with respect to one another. Accordingly, the inter-level capacitance C.sub.LS is made minimal. Conductors on the same level, however, must not cross over one another if shorting is to be avoided. As the circuit density increases, the spacing between conductors on the same level decreases. This provides concerns with respect to intra-level capacitance C.sub.LL. A challenge thereby exists to reduce die size yet maintain C.sub.LL as low as possible.
Increases in C.sub.LL parasitic capacitance pose two major problems. First, an increase in parasitic capacitance generally causes an increase in the time at which a transition on the one end of the conductor occurs at the other end. Increase in transition time (i.e., increase in speed degregation) thereby requires a longer drive period. If the conductor extends along a critical speed path, speed degregation on the line will jeopardize functionality of the overall circuit. Second, a larger parasitic capacitance causes an increase in crosstalk noise. A conductor which does not transition, nonetheless receives crosstalk noise from neighboring lines which do.
It is thereby important to minimize propagation delay especially in critical speed paths and/or between conductors which are spaced close to one another. Geometric constraints make it difficult to increase conductor thickness T.sub.c. or dielectric thickness T.sub.d2. Still further, instead of reducing length L of a conductor, most modern integrated circuits employ longer interconnect lines which compound the propagation delay problems. Accordingly, a need arises for reducing propagation delay and cross coupling by somehow maximizing dielectric thickness T.sub.d2 between conductors on the same level. More specifically the desired configuration must be one which provides maximum spacing between densely arranged conductors, or conductors in critical speed paths.